The accurate diagnosis of faults is an increasingly important aspect of testing integrated circuits, especially in view of ever-increasing gate counts and shrinking feature sizes. For circuits that do not utilize compression techniques during testing, fault diagnosis is relatively straightforward. For circuits that have embedded compression hardware, however, accurate fault diagnosis presents a formidable challenge.
The use of compression during the testing of integrated circuits has become widespread. In general, compression helps reduce the volume of test data required for even traditional stuck-at test sets. Such sets, for example, often exceed the capacity of automatic test equipment (“ATE”) used to test today's multimillion-gate integrated circuits. Moreover, due to the limited bandwidth between the circuit-under-test (“CUT”) and the ATE, the use of compressed test data and compressed test responses can decrease test time, and thus the test cost.
Automated fault diagnosis (e.g., diagnosis based on chain patterns and scan patterns obtained from automated test pattern generation (“ATPG”)) is a desirable component of an overall failure-analysis process. Automated fault diagnosis is generally used to predict the location of a failure in a CUT and has applications in such fields as silicon debugging, yield learning, and yield improvement. Given the failing test responses to a test set, an automated fault diagnosis tool desirably identifies the suspect fault sites that best explain the failures. The suspect sites identified can help locate the physical cause of the fault and be used to guide failure analysis at the physical level.